MPC7457 datasheet(51/68 Pages) FREESCALE

51 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits.

It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA

footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias.

Figure 24. PLL Power Supply Filter Circuit

NOTE

Previous revisions of this document required a 400

Ω resistor for Rev. 1.1 (Rev. B)

devices instead of the 10

Ω resistor shown above. All production devices require a

Ω resistor. For more information, see the MPC7450 Family Chip Errata for the

MPC7457 and MPC7447.

9.3

Decoupling Recommendations

Due to the MPC7457 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power supply,

especially while driving large capacitive loads. This noise must be prevented from reaching other components in the

MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pin

of the MPC7457. It is also recommended that these decoupling capacitors receive their power from separate VDD,

OVDD/GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. If compromises

must be made due to board constraints, VDD pins should receive the highest priority for decoupling.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors

should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along

the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design:

A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling

Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of

capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the

VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors

should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should

also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk

capacitors: 100–330 µ F (AVX TPS tantalum or Sanyo OSCON).

9.4

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level.

Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC

(no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the MPC7457.

If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and L3VSEL should be

connected to BVSEL; the remainder of the L3 interface may be left unterminated.

VDD

AVDD

Ω

2.2 µF

GND

Low ESL Surface Mount Capacitors

MPC7457 Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc

MPC7457 Datasheet(HTML) 51 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL