WM8980GEFLSLASHV datasheet(64/81 Pages) WOLFSON

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WM8980

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PP Rev 1.6 January 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

GPIO1SEL

000

CSB/GPIO1 pin function select:

000= input (CSB/jack detection:

depending on MODE setting)

001= reserved

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=logic 1

111=logic 0

GPIO1POL

GPIO1 Polarity invert

0=Non inverted

1=Inverted

GPIO

Control

5:4

OPCLKDIV

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

2:0

GPIO4SEL

000

GPIO4 pin function select:

000= input jack detection

001= reserved

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=logic 1

111=logic 0

GPIO

Control

GPIO4POL

GPIO4 Polarity invert

0=Non inverted

1=Inverted

Table 53 CSB/GPIO Control

Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the

GPIO1SEL[2:] bits.

For further details of the Jack detect operation see the OUTPUT SWITCHING section.

OUTPUT SWITCHING (JACK DETECT)

When the device is configured with a 2-wire interface the CSB/GPIO1 pin can be used as a switch

control input to automatically disable one set of outputs and enable another.

The L2/GPIO2,

R2/GPIO3 and GPIO4 pins can also be used for this purpose. For example, when a headphone is

plugged into a jack socket then it may be desirable to disable the speaker (e.g. when one of the

GPIO pins is connected to a mechanical switch in the headphone socket to detect plug-in).

The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output

enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a

slow clock with period 2

21 x MCLK.

Note that the GPIOPOL bits are not relevant for jack detection, it is the signal detected at the pin

which is used.

The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2,

OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and

OUT4_EN_0 are the output enable signal which are used if the selected jack detection pin is at logic

0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output

enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).

WM8980GEFL/V Datasheet(PDF) 64 Page - Wolfson Microelectronics plc

WM8980GEFL/V Datasheet(HTML) 64 Page - Wolfson Microelectronics plc

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