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WM8980GEFL/V Datasheet(PDF) 68 Page - Wolfson Microelectronics plc |
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WM8980GEFL/V Datasheet(HTML) 68 Page - Wolfson Microelectronics plc |
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68 / 81 page  WM8980 Product Preview w PP Rev 1.6 January 2005 68 POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 DAC control 3 DACOSR128 0 DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) R14 ADC control 3 ADCOSR128 0 ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Table 56 ADC and DAC Oversampling Rate Selection VMID The analogue will not work unless VMID is enabled (VMIDSEL 00). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 1:0 VMIDSEL 00 Reference string impedance to VMID pin (detemines startup time): 00=off (open circuit) 01=75kΩ 10=300kΩ 11=5kΩ (for fastest startup) Table 57 VMID Impedance Control BIASEN The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 3 BIASEN 0 Analogue amplifier bias control Table 58 Analogue Bias Control ESTIMATED SUPPLY CURRENTS When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD. It is anticipated that the video buffer will draw about 1mA with no load attached, in normal operating up to 30 mA will be drawn. |
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