AD7771 datasheet(46/99 Pages) AD

46 / 99 page

Data Sheet

AD7771

Rev. 0 | Page 45 of 98

In SPI control mode, there are four different levels of input/

output (I/O) strength on the SDO pin that can be selected in

GENERAL_USER_CONFIG_2, Bits[4:3], as described in Table 23.

Table 23. SDO Strength

GENERAL_USER_CONFIG_2, Bits[4:3] Setting

Mode

Nominal

Strong

Weak

Extra strong

SCLK is the serial clock input for the device. All data transfers

(on either SDO or SDI) occur with respect to this SCLK signal.

The SPI can operate in multiples of eight bits. For example, in

SPI control mode, if the SDO pin is used to read back the data

from the internal register or the SAR ADC, the data frame is

16 bits wide (CRC disabled), as shown in Figure 118, or 24 bits

wide (CRC enabled), as shown in Figure 119. In this case, the

controller can generate one frame of 16 bits or 24 bits (with and

without the CRC enabled), or two or three frames of 8 bits (with

and without the CRC enabled). When the SDO pin reads back

the data from the Σ-Δ channels, 64 bits must be read back from

the controller (in this case, the controller can generate a frame

of 64 bits—either 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits).

SPI CRC—Checksum Protection (SPI Control Mode)

The AD7771 has a checksum mode that improves SPI

robustness in SPI control mode. Using the checksum ensures

that only valid data is written to a register and allows data read

from the device to be validated. The SPI CRC can be enabled by

setting the SPI_CRC_TEST_EN bit. If an error occurs during a

Enabling the SPI_CRC_TEST_EN bit results in a CRC checksum

being performed on all the R/W operations. When SPI_CRC_

TEST_EN is enabled, an 8-bit CRC word is appended to every

SPI transaction for SAR and register map operations. For more

information on Σ-Δ readback operations, see the CRC Header

section.

To ensure that the register write is successful, it is recommended to

read back the register and verify the checksum.

For CRC checksum calculations, the following polynomial is

always used: x8 + x2 + x + 1. See the SPI Control Mode Checksum

section for more information.

SPI Read/Write Register Mode (SPI Control Mode)

The AD7771 has on-board registers to configure and control

the device.

The registers have 7-bit addresses—the 7-bit register address on

the SDI line selects the register for the read/write function. The

7-bit register address follows the R/W bit in the SDI data. The

8 bits on the SDI line following the 7-bit register address are the

data to be written to the selected register if the SPI is a write

transfer. Data on the SDI line is clocked into the AD7771 on

the rising edge of SCLK, as shown in Figure 3.

The data on the SDO line during the SPI transfer contains the

8-bit 0010 0000 header: 8 bits of register data in the case of a read

(R) operation, or 8 zeros in the case of a write (W) operation.

With the CRC disabled, the basic data frame on the SDI line

during the transfer is 16 bits long, as shown in Figure 118.

When the CRC is enabled, a minimum frame length of 24 SCLK

periods are required on SPI transfers. The 24 bits of data on the

SDO line consist of an 8-bit header (0010 0000), 8 bits of data, and

an 8-bit CRC (see Figure 119).

R/W A6

SDO

SCLK

SDI

Figure 118. 16-Bit SPI Transfer—CRC Disabled

R/W A6

D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0

SDO

SCLK

SDI

R0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0

Figure 119. 24-Bit SPI Transfer—CRC Enabled

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