AD6673 datasheet(24/46 Pages) AD

24 / 46 page

Data Sheet

AD6673

Rev. C | Page 23 of 45

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 42, the power dissipated by the AD6673 is

proportional to its sample rate. The data in Figure 42 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

140

190

240

POWER (AVDD)

POWER (DVDD + DRVDD)

TOTAL POWER

ENCODE FREQUENCY (MSPS)

Figure 42. AD6673-250 Power vs. Encode Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD6673 is placed in power-down mode.

In this state, the ADC typically dissipates about 9 mW. Asserting the

PDWN pin low returns the AD6673 to its normal operating mode.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Description section and the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI, for additional details.

AD6673 Datasheet(PDF) 24 Page - Analog Devices