AR0141CS datasheet(44/48 Pages) ONSEMI

44 / 48 page

AR0141CS

www.onsemi.com

Figure 47. Eye Diagram for Clock and Data Signals

UI/2

TxPre

TxPost

CLOCK MASK

RISE

FALL

20%

80%

CLK JITTER

Trigger/Reference

DATA MASK

Figure 48. HiSPi Skew Between Data Signals Within the PHY

tCHSKEW1PHY

Table 33.

CHANNEL, PHY, AND INTRA−PHY SKEW

(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data DLL set to 0)

Data Lane Skew in Reference to Clock

tCHSKEW1PHY

−150

Table 34.

CLOCK DLL STEPS

(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data DLL set to 0)

Clock DLL Step

Step

Delay at 660 Mbps

0.25

0.375

0.5

0.625

0.75

Eye_opening at 660 Mbps

0.85

0.78

0.71

0.69

1. The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0141CS.

Table 35.

DATA DLL STEPS

(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data DLL set to 0)

Data DLL Step

Step

Delay at 660 Mbps

0.25

0.375

0.625

0.875

Eye opening at 660 Mbps

0.79

0.84

0.71

0.61

1. The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0141CS.

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