OX16CF950 datasheet(43/60 Pages) ETC

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OXCF950 DATA SHEET V1.1

OXFORD SEMICONDUCTOR LTD.

value of 0x00 is illegal.

For example if FCL and FCH contain 64 and 100

respectively, XOFF is transmitted when the receiver FIFO

contains 100 characters, and XON is transmitted when

sufficient characters are read from the receiver FIFO such

that there are 63 characters remaining.

CTS/RTS and DSR/DTR out-of-band flow control use the

same trigger levels as in-band flow control. When out-of-

band flow control is enabled, RTS# (or DTR#) line is de-

asserted when the receiver FIFO level reaches the upper

limit defined in the FCH and is re-asserted when the

receiver FIFO is drained below the lower limit defined in

FCL. When 950 trigger levels are enabled (ACR[5]=1), the

CTS# flow control functions as in 650 mode and is

configured by EFR[7]. However, when EFR[6] is set, RTS#

is automatically de-asserted when RFL reaches FCH and

re-asserted when RFL drops below FCL.

DSR# flow control is configured with ACR[2]. DTR# flow

control is configured with ACR[4:3].

6.11.7 Device Identification Registers

The identification registers is located at offsets 0x08 to 0x0B

of the ICR

The 950 offers four bytes of device identification. The

device ID registers may be read using offset values 0x08 to

0x0B of the Indexed Control Register. Registers ID1, ID2

and ID3 identify the device as an OX16C950 type and

return 0x16, 0xC9 and 0x50 respectively. The REV register

resides at offset 0x0B of ICR and identifies the revision of

950 core. This register returns 0x06 for the OXCF950.

6.11.8 Clock Select Register ‘CKS’

The CKS register is located at offset 0x03 of the ICR

This register is cleared to 0x00 after a hardware reset to

maintain compatibility with 16C550, but is unaffected by

software reset. This allows the user to select a clock

source and then reset the channel to work-around any

timing glitches.

CKS[1:0]: Receiver Clock Source Selector

logic [00] ⇒ The output of baud rate generator (internal

BDOUT#) is selected for the receiver clock.

logic [01] ⇒ The DSR# pin is selected for the receiver

clock.

logic [10] ⇒ The output of baud rate generator (internal

BDOUT#) is selected for the receiver clock.

logic [11] ⇒ The transmitter clock is selected for the

receiver. This allows RI# to be used for both

transmitter and receiver.

CKS[2]: Reserved

This bit is unused in the OXCF950 and should be written

with ‘0’.

CKS[3]: Receiver 1x clock mode selector

logic 0 ⇒

The receiver is in Nx clock mode as defined

in the TCR register. After a hardware reset

the receiver operates in 16x clock mode, i.e.

16C550 compatibility.

logic 1 ⇒

The receiver is in isochronous 1x clock

mode.

CKS[5:4]: Transmitter 1x clock or baud rate generator

output (BDOUT) on DTR# pin

logic [00] ⇒ The function of the DTR# pin is defined by

the setting of ACR[4:3].

logic [01] ⇒ The transmitter 1x clock (bit rate clock) is

asserted on the DTR# pin and the setting of

ACR[4:3] is ignored.

logic [10] ⇒ The output of baud rate generator (Nx clock)

is asserted on the DTR# pin and the setting

of ACR[4:3] is ignored.

logic [11] ⇒ Reserved.

CKS[6]: Transmitter clock source selector

logic 0 ⇒

The transmitter clock source is the output of

the baud rate generator (550 compatibility).

logic 1 ⇒

The transmitter uses an external clock

applied to the RI# pin.

CKS[7]: Transmitter 1x clock mode selector

logic 0 ⇒

The transmitter is in Nx clock mode as

defined in the TCR register. After a

hardware reset the transmitter operates in

16x clock mode, i.e. 16C550 compatibility.

logic 1 ⇒

The transmitter is in isochronous 1x clock

mode.

6.11.9 Nine-bit Mode Register ‘NMR’

The NMR register is located at offset 0x0D of the ICR

The 950 offers 9-bit data framing for industrial multi-drop

applications. 9-bit mode is enabled by setting bit 0 of the

Nine-bit Mode Register (NMR). In 9-bit mode the data

length setting in LCR[1:0] is ignored. Furthermore as parity

is permanently disabled, the setting of LCR[5:3] is also

ignored.

The receiver stores the 9th bit of the received data in

LSR[2] (where parity error is stored in normal mode). Note

that the 950 provides a 128-deep FIFO for LSR[3:1]. The

transmitter FIFO is 9-bit wide and 128 deep. The user

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