ATECC508A datasheet(34/109 Pages) MICROCHIP

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General I/O Information

Communications to the ATECC508A are through one of two different protocols. The protocols are

selected by specifying the part number that is ordered:

•

Single-Wire Interface: Uses a single GPIO connection on the system microprocessor that is

connected to the SDA pin on the device. It permits the fewest number of pins connected to any

removable or replaceable entity. The bit rate is up to 26Kb/s.

•

I2C Interface: This mode is compatible with the I2C standard and also with the Microchip AT24C16

Serial EEPROM interface. Two pins, Serial Data (SDA) and Serial Clock (SCL), are required. The

I2C interface supports a bit rate of up to 1Mb/s.

Note: The ATECC508A and AT24C16B have different default I2C addresses. The ATECC508A

I2C address can be modified from default by writing a new value into the configuration zone.

The lowest levels of the I/O protocols are described below. Above the I/O protocol level, exactly the same

bytes are transferred to and from the device to implement the security commands and error codes, which

are documented in section Security Commands.

Note: The device implements a fail-safe internal watchdog timer that forces it into a very low power

mode after a certain time interval regardless of any current activity. System programming must take this

into consideration. See section Watchdog Failsafe.

4.1

Byte and Bit Ordering

CryptoAuthentication uses a common ordering scheme for bytes and also for the way in which numbers

and arrays are represented in this datasheet:

•

All multi-byte aggregate elements are treated as arrays of bytes and are processed in the order

received or transmitted with index #0 first.

•

16 bit (2 byte) integers, typically Param2, SlotConfig or KeyConfig, appear on the bus least-

significant byte first.

•

ECC keys appear on the bus, and are stored in EEPROM, with the most significant 32-bit word at

the lowest address. See Section ECC Key Formatting for further information on ECC key

formatting.

In this document, the most-significant bit or nibble of a byte or 16-bit word appears towards the left hand

side of the page.

The bit order is different depending upon the I/O channel used:

•

On the one-wire bus, data is transferred to and from the ATECC508A Least Significant bit (LSb)

first on the bus.

•

On the I2C interface, data is transferred to and from the ATECC508A Most Significant bit (MSb) first

on the bus.

4.1.1

ECC Key Formatting

The format for public and private keys depends on the command and key length. In general, the Most

Significant Bytes (MSB) appear first on the bus and at the lowest address in memory. In the remainder of

this section, the bytes on the left side of the page are the MSBs. Microchip recommends all pad bytes be

set to zero for consistency.

•

ECC private keys appear to the user only as the input parameter to the PrivWrite command.

This parameter is always 36 bytes in length and the first four bytes (32 bits) are all pad bits.

ATECC508A

General I/O Information

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