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LAN9220 Datasheet(PDF) 30 Page - Microchip Technology

Part # LAN9220
Description  16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
PDF  142 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9220 Datasheet(HTML) 30 Page - Microchip Technology

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LAN9220
DS00002417A-page 30
 2006-2017 Microchip Technology Inc.
3.9
EEPROM Interface
The LAN9220 can optionally load its MAC address from an external serial EEPROM. If a properly configured EEPROM
is detected by the LAN9220 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be loaded with
the contents of the EEPROM. If a properly configured EEPROM is not detected, it is the responsibility of the host LAN
Driver to set the IEEE addresses.
The LAN9220 EEPROM controller also allows the host system to read, write and erase the contents of the Serial
EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation.
3.9.1
MAC ADDRESS AUTO-LOAD
On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data from the EEPROM
(address 00h). If the value A5h is read from the first address, then the EEPROM controller will assume that an external
Serial EEPROM is present. The EEPROM controller will then access the next EEPROM byte and send it to the MAC
Address register byte 0 (ADDRL[7:0]). This process will be repeated for the next five bytes of the MAC Address, thus
fully programming the 48-bit MAC address. Once all six bytes have been programmed, the “MAC Address Loaded” bit
is set in the E2P_CMD register. A detailed explanation of the EEPROM byte ordering with respect to the MAC address
is given in Section 5.4.3, "ADDRL—MAC Address Low Register," on page 96.
If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. It is then the responsibility
of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers.
The host can initiate a reload of the MAC address from the EEPROM by issuing the RELOAD command via the E2P
command (E2P_CMD) register. If the first byte read from the EEPROM is not A5h, it is assumed that the EEPROM is
not present, or not programmed, and the MAC address reload will fail. The “MAC Address Loaded” bit indicates a suc-
cessful reload of the MAC address.
3.9.2
EEPROM HOST OPERATIONS
After the EEPROM controller has finished reading (or attempting to read) the MAC after power-on, hard reset or soft
reset, the host is free to perform other EEPROM operations. EEPROM operations are performed using the E2P_CMD
and E2P data (E2P_DATA) registers. Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 89 provides
an explanation of the supported EEPROM operations.
If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the host must first write the
desired data into the E2P_DATA register. The host must then issue the WRITE or WRAL command using the E2P_CMD
register by setting the EPC_CMD field appropriately. If the operation is a WRITE, the EPC_ADDR field in E2P_CMD
must also be set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The com-
pletion of the operation is indicated when the EPC_BSY bit is cleared.
If the EEPROM operation is the “read location” (READ) operation, the host must issue the READ command using the
E2P_CMD with the EPC_ADDR set to the desired location. The command is executed when the host sets the EPC_BSY
bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared, at which time the data from the
EEPROM may be read from the E2P_DATA register.
Other EEPROM operations are performed by writing the appropriate command to the EPC_CMD register. The com-
mand is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the
EPC_BSY bit is cleared. In all cases the host must wait for EPC_BSY to clear before modifying the E2P_CMD register.
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9220 will timeout, and the
EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3-10, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an EEPROM Read or
Write operation.
Note:
The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM
the host must first issue the EWEN command.



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