LAN9220 datasheet(9/142 Pages) MICROCHIP

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 2006-2017 Microchip Technology Inc.

DS00002417A-page 9

LAN9220

2.1

Pin List

TABLE 2-1:

HOST BUS INTERFACE SIGNALS

Name

Symbol

Buffer

Type

Pins

Description

Host Data

D[15:0]

VIS/VO8

Bi-directional data port.

Host Address

A[7:1]

VIS

7-bit Address Port. Used to select Internal CSR’s and

TX and RX FIFOs.

Read Strobe

nRD

VIS

Active low strobe to indicate a read cycle.

Write Strobe

nWR

VIS

Active low strobe to indicate a write cycle. This signal,

qualified with nCS, is also used to wakeup the

LAN9220 when it is in a reduced power state.

Chip Select

nCS

VIS

Active low signal used to qualify read and write

operations. This signal qualified with nWR is also used

to wakeup the LAN9220 when it is in a reduced power

state.

Interrupt

Request

IRQ

VO8/

VOD8

Programmable Interrupt request. Programmable

polarity, source and buffer types.

FIFO Select

FIFO_SEL

VIS

When driven high all accesses to the LAN9220 are to

the RX or TX Data FIFOs. In this mode, the A[7:3]

upper address inputs are ignored.

TABLE 2-2:

LAN INTERFACE SIGNALS

Name

Symbol

Buffer

Type

# Pins

Description

TPO+

Transmit Positive Output (normal)

Receive Positive Input (reversed)

TPO-

Transmit Negative Output (normal)

Receive Negative Input (reversed)

TPI+

Receive Positive Input (normal)

Transmit Positive Input (reversed)

TPI-

Receive Negative Input (normal)

Transmit Negative Output (reversed)

PHY External Bias

Resistor

EXRES

Must be connected to ground through a 12.4K

ohm 1% resistor.

Note:

The pin names for the twisted pair pins shown above apply to a normal connection. If HP Auto-MDIX is

enabled and a reverse connection is detected, or a reverse connection is manually selected, the input pins

become outputs, and vice-versa, as indicated in the descriptions.

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