MB90347CEPMC datasheet(67/93 Pages) CYPRESS

67 / 93 page

Document Number: 002-04498 Rev. *A

Page 66 of 92

MB90340E Series



Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0

(TA  40°C to 105°C, VCC  5.0 V  10, fCP 24 MHz, VSS  0 V)

Note:

 C

L is load capacity value of pins when testing.

 t

CP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Parameter

Symbol

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK0 to SCK3

Internal shift clock

mode output pins are

 80 pF  1 TTL.

5 tCP



SCK

  SOT delay time

tSHOVI

SCK0 to SCK3,

SOT0 to SOT3

50

50

Valid SIN

 SCK 

tIVSLI

SCK0 to SCK3,

SIN0 to SIN3

tCP + 80



SCK

  Valid SIN hold time

tSLIXI

SCK0 to SCK3,

SIN0 to SIN3



Serial clock “H” pulse width

tSHSL

SCK0 to SCK3

External shift clock

mode output pins are

 80 pF  1 TTL.

3 tCP - tR 

Serial clock “L” pulse width

tSLSH

SCK0 to SCK3

tCP + 10



SCK

  SOT delay time

tSHOVE

SCK0 to SCK3,

SOT0 to SOT3



2 tCP + 60

Valid SIN

 SCK 

tIVSLE

SCK0 to SCK3,

SIN0 to SIN3



SCK

  Valid SIN hold time

tSLIXE

SCK0 to SCK3,

SIN0 to SIN3

tCP + 30



SCK fall time

SCK0 to SCK3



SCK rise time

SCK0 to SCK3



 External Shift Clock Mode

SCK0 to SCK3

VIH

VIL

SOT0 to SOT3

0.8 V

2.4 V

tSLOVE

SIN0 to SIN3

VIL

VIH

VIL

VIH

VIL

tSHSL

tSLSH

tIVSHE

tSHIXE

MB90347CEPMC Datasheet(PDF) 67 Page - Cypress Semiconductor

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