MB90347CEPMC datasheet(69/93 Pages) CYPRESS

69 / 93 page

Document Number: 002-04498 Rev. *A

Page 68 of 92

MB90340E Series



Bit setting: ESCR:SCES

 0, ECCR:SCDE  1

(TA  40°C to 105°C, VCC  5.0 V  10, fCP 24 MHz, VSS  0 V)

Note:

 C

L is load capacity value of pins when testing.

 t

CP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Parameter

Symbol

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK0 to SCK3

Internal clock operation output

pins are

 80 pF  1 TTL.

5 tCP



SCK

  SOT delay time

tSHOVI

SCK0 to SCK3,

SOT0 to SOT3

50

50

Valid SIN

 SCK 

tIVSLI

SCK0 to SCK3,

SIN0 to SIN3

tCP  80



SCK

  Valid SIN hold time

tSLIXI

SCK0 to SCK3,

SIN0 to SIN3



SOT

 SCK  delay time

tSOVLI

SCK0 to SCK3,

SOT0 to SOT3

3 tCP  70



SCK0 to SCK3

2.4 V

tSCYC

0.8 V

SOT0 to SOT3

0.8 V

2.4 V

tSOVLI

SIN0 to SIN3

VIL

VIH

tIVSLI

VIL

VIH

tSLIXI

0.8 V

tSHOVI

0.8 V

2.4 V

MB90347CEPMC Datasheet(PDF) 69 Page - Cypress Semiconductor

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