MB90347CEPMC datasheet(70/93 Pages) CYPRESS

70 / 93 page

Document Number: 002-04498 Rev. *A

Page 69 of 92

MB90340E Series



Bit setting: ESCR:SCES

 1, ECCR:SCDE  1

(TA  40°C to 105°C, VCC  5.0 V  10, fCP 24 MHz, VSS  0 V)

Note:

 C

L is load capacity value of pins when testing.

 t

CP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Parameter

Symbol

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK0 to SCK3

Internal clock operation

output pins are

 80 pF  1 TTL.

5 tCP



SCK

  SOT delay time

tSLOVI

SCK0 to SCK3,

SOT0 to SOT3

50

50

Valid SIN

 SCK 

tIVSHI

SCK0 to SCK3,

SIN0 to SIN3

tCP  80



SCK

  Valid SIN hold time

tSHIXI

SCK0 to SCK3,

SIN0 to SIN3



SOT

 SCK  delay time

tSOVHI

SCK0 to SCK3,

SOT0 to SOT3

3 tCP  70



SCK0 to SCK3

2.4 V

tSCYC

2.4 V

SOT0 to SOT3

0.8 V

2.4 V

tSOVHI

SIN0 to SIN3

VIL

VIH

tIVSHI

VIL

VIH

tSHIXI

0.8 V

tSLOVI

0.8 V

2.4 V

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