LTM2893 datasheet(16/32 Pages) LINER

16 / 32 page

LTM2893/LTM2893-1

28931fb

For more information www.linear.com/LTM2893

APPLICATIONS INFORMATION

Table 2. BUSY Fall to SCK Rising Delay Required for Major

Word Boundaries to Operate at Maximum SCK Under Worst

Case SCK2 Tolerance

tBUSYFSCKR

TOTAL NUMBER OF BITS PER SPI TRANSACTION

SCKMAX

128

100MHz

15ns

41ns

67ns

93ns

66MHz

22ns

62ns

100ns

140ns

50MHz

29ns

81ns

133ns

186ns

40MHz

36ns

102ns

167ns

232ns

33MHz

44ns

124ns

202ns

282ns

25MHz

58ns

162ns

267ns

370ns

12.5MHz

120ns

324ns

532ns

739ns

6.25MHz

229ns

644ns

1062ns

1476ns

Add time delay to the Master FPGA or microcontroller

between the BUSY fall and the first SCK in order to operate

SCKattheconfiguredSCK2frequency.AminimumtSSFSCK

of 15ns is required in the timing specifications between a

fall of SS and the first SCK or the fall of BUSY and the first

SCK if SS is always low. Referencing Table 2, under most

cases with a single or a pair of parallel devices connected

to the LTM2893, the minimum or a single SCK period is

required between the BUSY falling edge and the rising

edge of the first SCK to support the maximum operating

frequency. As the WORDLENGTH and DEVICECOUNT

increases, the tBUSYFSCKR must be increased if operating

near the maximum SCK.

CYCLIC REDUNDANCY CHECK (CRC)

The CRC enable selection bit (Config Register 0, bit 3)

enables an internal CRC process to be completed during

thecommunicationofSPIdataacrosstheinternalisolation

barrier. The CRC is a 3-bit message added to the end of a

SPIdatawordandischeckedonthereceiverside.TheCRC

is an internal function and the values are not readable. If

the check fails, the FAULT pin is asserted low. When CRC

is enabled, an additional wait of 225ns is required for the

CRC to complete processing before the reassertion of a

new SPI transaction or a new rising edge on CNV.

DEVICECOUNT AND WORDLENGTH

TheDEVICECOUNTconfigurationbitsselectthenumberof

wordstheLTM2893willprocess.Theselectionofthisvalue

is based on the number of ADCs isolated or the number

of words that must be written or read from the ADC. The

DEVICECOUNT selection is used in conjunction with the

WORDLENGTH selection bits. The WORDLENGTH is set

to the number of bits per word. The WORDLENGTH selec-

tion allows the SPI access to be tailored to a specific ADC

result length to maximize throughput. When a controller

that requires byte wide increments is used, set the word

length to the number of bits on a byte size boundary (8,

16, 24, or 32). The total number of bits per SPI transac-

tion is the WORD COUNT • WORDLENGTH as referenced

in Table 6 and Table 7.

For example, a single 16-bit ADC is selected as DEVICE-

COUNT of 1-2 with a WORDLENGTH of 16. Two 16 bit

ADCs in parallel (SDO of ADC1 connected to MISOA2 and

SDO of ADC2 connected to MISOB2) are also selected as a

DEVICECOUNT of 1-2 with a word length of 16. Chaining

a device increases the DEVICECOUNT. Chaining two ad-

ditional ADCs through the first pair of ADCs would change

the DEVICECOUNT to 3-4 with a word-length of 16.

The DEVICECOUNT is interchangeable with the number of

words, WORD COUNT, a device requires for communica-

tion. An example ADC may need 4 words of 32 bits. In this

case, selecting the maximum DEVICECOUNT of 7-8 will

write or read 4 words and setting the WORDLENGTH to

32 will set the length of each word. The LTM2893 writes

or reads ½ the number of words as the DEVICECOUNT

value. WORD COUNT is equal to ½ of DEVICECOUNT,

see Table 7. A DEVICECOUNT of 1-2 will read 1 word, a

DEVICECOUNT of 3-4 will read 2 words, a DEVICECOUNT

of 5-6 will read 3 words, and a DEVICECOUNT of 7-8 will

read 4 words.

LTM2893-1 ADC READ/WRITE

The LTM2893-1 writes a SPI word to the isolated ADC

after the read operation. On the logic side, a SPI transac-

tion will output data from MISOA, MISOB and read in a

command for the ADC in the MOSI pin. At start-up, prior

LTM2893 Datasheet(PDF) 16 Page - Linear Technology

LTM2893 Datasheet(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL