S29CD032G datasheet(26/93 Pages) SPANSION

26 / 93 page

S29CD032G

30606B0 March 22, 2004

Ad va n c e

In f o rm a t i o n

CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)

Speed Options 54D, 64C, 65A:

0000 = 2 CLK cycle initial burst access delay

0001 = 3 CLK cycle initial burst access delay

0010 = 4 CLK cycle initial burst access delay

0011 = 5 CLK cycle initial burst access delay

0100 = 6 CLK cycle initial burst access delay

0101 = 7 CLK cycle initial burst access delay

0110 = 8 CLK cycle initial burst access delay

0111 = 9 CLK cycle initial burst access delay—Default

CR9 = Data Output Configuration (DOC)

0 = Hold Data for 1-CLK cycle—Default

1 = Reserved

CR8 = IND/WAIT# Configuration (WC)

0 = IND/WAIT# Asserted During Delay—Default

1 = IND/WAIT# Asserted One Data Cycle Before Delay

CR7 = Burst Sequence (BS)

0 = Reserved

1 = Linear Burst Order—Default

CR6 = Clock Configuration (CC)

0 = Reserved

1 = Burst Starts and Data Output on Rising Clock Edge—Default

CR5–CR3 = Reserved For Future Enhancements (R)

These bits are reserved for future use. Set these bits to “0.”

CR2–CR0 = Burst Length (BL2–BL0)

000 = Reserved, burst accesses disabled (asynchronous reads only)

001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear

010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear

011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)

100 = Reserved, burst accesses disabled (asynchronous reads only)

101 = Reserved, burst accesses disabled (asynchronous reads only)

110 = Reserved, burst accesses disabled (asynchronous reads only)

Table 9. Configuration Register Definitions (Continued)

S29CD032G Datasheet(PDF) 26 Page - SPANSION