S29CD032G datasheet(14/93 Pages) SPANSION

14 / 93 page

S29CD032G

30606B0 March 22, 2004

Ad va n c e

In f o rm a t i o n

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is com-

posed of latches that store the commands, along with the address and data

information needed to execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus operations, the inputs and con-

trol levels they require, and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Device Bus Operation

Legend:

L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care.

Notes:

1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.

2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB

Operation

CE#

OE#

WE#

RESET#

CLK

ADV#

Addresses

Data

(DQ0–DQ31)

Read

AIN

DOUT

Asynchronous Write

AIN

DIN

Synchronous Write

AIN

DIN

Standby (CE#)

HIGH Z

Output Disable

HIGH Z

Reset

HIGH Z

PPB Protection Status (Note 2)

Sector Address,

A9 = VID,

A7 – A0 = 02h

00000001h,

(protected)

A6 = H

00000000h

(unprotect)

A6 = L

Burst Read Operations

Load Starting Burst Address

AIN

Advance Burst to next address

with appropriate Data

presented on the Data bus

Burst Data Out

Terminate Current Burst Read

Cycle

HIGH Z

Terminate Current Burst Read

Cycle with RESET#

HIGH Z

Terminate Current Burst Read

Cycle; Start New Burst Read

Cycle

AIN

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