X5083

FN8127 Rev 4.00

Page 3 of 21

November 12, 2015

Pin Description

Ordering Information

PART NUMBER RESET (ACTIVE LOW)

(Note 1)

PART

MARKING

(V)

(V)

TEMPERATURE

RANGE (°C)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

X5083PIZ-4.5A (No longer available or

supported)

X5083P ZAM

4.5-5.5

4.5-4.75

-40 to 85

8 Ld PDIP*

MDP0031

X5083S8Z-4.5A

X5083 ZAL

0 to 70

8 Ld SOIC

M8.15E

X5083S8IZ-4.5A (Note 2)

X5083 ZAM

-40 to 85

8 Ld SOIC

M8.15E

X5083S8Z

X5083 Z

4.5-5.5

4.25-4.5

0 to 70

8 Ld SOIC

M8.15E

X5083S8IZ (Note 2)

X5083 ZI

-40 to 85

8 Ld SOIC

M8.15E

X5083V8IZ (No longer available,

recommended replacement:

X5083S8IZ)

583 IZ

-40 to 85

8 Ld TSSOP

M8.173

X5083S8Z-2.7A

X5083 ZAN

2.7-5.5

2.85-3.0

0 to 70

8 Ld SOIC

M8.15E

X5083S8IZ-2.7A*

X5083 ZAP

-40 to 85

8 Ld SOIC

M8.15E

X5083S8Z-2.7*

X5083 ZF

2.7-5.5

2.55-2.7

0 to 70

8 Ld SOIC

M8.15E

X5083S8IZ-2.7*

X5083 ZG

-40 to 85

8 Ld SOIC

M8.15E

X5083V8IZ-2.7 (No longer available,

recommended replacement:

X5083S8IZ-2.7)

583 GZ

-40 to 85

8 Ld TSSOP

M8.173

NOTE:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. *Add "-T1" suffix for tape and reel.

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

PIN

(SOIC/

PDIP)

PIN

TSSOP

NAME

FUNCTION

13

CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a

nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device,

placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition

on CS is required.

Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH

to LOW transition within the watchdog time out period results in RESET going active.

24

SO

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the

serial clock (SCK) clocks the data out.

57

SI

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge

of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.

68

SCK

Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in

the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.

35

WP

Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the

memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.

46

Ground

82

Supply Voltage

7

1

RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable

watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power-up at

about 1V and remains active for 250ms after the power supply stabilizes.