SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016

Freescale Semiconductor, Inc.

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1.2. Features

1.2.1. i.MX 6Dual/6Quad Features

The i.MX 6Dual/6Quad processors are based on ARM® Cortex®-A9 MPCore platform, which has the

following features:

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ARM Cortex-A9 MPCore 4xCPU processor (with TrustZone®)

•

The core configuration is symmetric, where each core includes:

— 32 Kbyte L1 Instruction Cache

— 32 Kbyte L1 Data Cache

— Private Timer and Watchdog

— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The ARM Cortex-A9 MPCore complex includes:

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General Interrupt Controller (GIC) with 128 interrupt support

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Global Timer

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Snoop Control Unit (SCU)

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1 MB unified I/D L2 cache, shared by two/four cores

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Two Master AXI (64-bit) bus interfaces output of L2 cache

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Frequency of the core (including Neon and L1 cache) as per Table 4-3

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NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)

— Secure/non-secure RAM (16 KB)

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External memory interfaces:

— 32-bit LPDDR2, supporting DDR interleaving mode, or fixed 2x32.

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page

size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to

40 bits.