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AD9530 Datasheet(PDF) 11 Page - Analog Devices

Part # AD9530
Description  4 CML Output, Low Jitter Clock Generator
PDF  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9530 Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD9530
Rev. 0 | Page 11 of 41
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SDIO (INPUT)
Input Voltage
Logic 1
VDD − 0.4
V
Logic 0
0.4
V
Input Current
Logic 1
1
µA
Logic 0
1
µA
Input Capacitance
3
pF
SDIO, SDO (OUTPUTS)
1 mA load current
Output Voltage
Logic 1
VDD − 0.2
V
Logic 0
0.2
V
TIMING
See Figure 26 through Figure 30 and Table 21
Clock Rate (SCLK)
1/tSCLK
40
MHz
Pulse Width High
tHIGH
6
ns
Pulse Width Low
tLOW
6
ns
SDIO to SCLK Setup
tDS
1.8
ns
SCLK to SDIO Hold
tDH
0.6
ns
SCLK to Valid SDIO and SDO
tDV
10
ns
CS to SCLK Setup
tS
0.6
ns
CS to SCLK Hold
tH
3.5
ns
CS Minimum Pulse Width High
tPWH
1.5
ns



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