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AD9530 Datasheet(PDF) 28 Page - Analog Devices

Part # AD9530
Description  4 CML Output, Low Jitter Clock Generator
PDF  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9530 Datasheet(HTML) 28 Page - Analog Devices

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AD9530
Data Sheet
Rev. 0 | Page 28 of 41
TYPICAL APPLICATION BLOCK DIAGRAM
FPGA/ASIC
FRAMER/
PHY
NPU
TRAFFIC
MANAGEMENT
FRAMER/
FEC
AD9554
(QUAD CHANNEL DPLL)
AD9530
10 × 10Gbps
10 × 10Gbps
OPTICAL
MODULE
HIGH
SPEED
Tx DAC
OPTICAL
FRONT
END
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
TO NETWORK
3 ×
AD9554-1
(QUAD CHANNEL
DPLL)
10Gbps SERDES
TRx
MODULES
FPGA/ASIC
FRAMER/
PHY
NPU
TRAFFIC
MANAGEMENT
DEMAPPING
CONTROL
FRAMER/
FEC
AD9554
(QUAD CHANNEL DPLL)
AD9530
10 × 10Gbps
10 × 10Gbps
OPTICAL
MODULE
HIGH
SPEED
Tx DAC
OPTICAL
FRONT
END
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
FROM NETWORK
Figure 33. Typical Application Block Diagram, 100 Gbps Muxponder with the AD9530



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