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S29AL032D Datasheet(PDF) 29 Page - SPANSION

Part # S29AL032D
Description  32 Megabit CMOS 3.0 Volt-only Flash Memory
PDF  69 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S29AL032D Datasheet(HTML) 29 Page - SPANSION

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June 13, 2005 S29AL032D_00_A3
S29AL032D
27
Ad vance
Info rmat i o n
without raising any device pin to a high voltage. Note that this method is only applicable to
the Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm
shown in Figure 3, on page 27.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to reading and writing the remainder of the
array.
The Secured Silicon Sector protection must be used with caution since, once protected, there is
no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in
the Secured Silicon Sector memory space can be modified in any way.
Figure 3. Secured Silicon Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (refer to Table 17 on page 38 for command definitions). In
addition, the following hardware data protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
START
RESET# =
VIH or VID
Wait 1
μs
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove VIH or VID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete



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