FS9912

Rev. 3.6

16/34

Example 2

16-bit add: {M (83h), M (82h)} = {M (83h), M (82h)} + {M (81h), M (80h)}

16-bit sub: {M (83h), M (82h)} = {M (83h), M (82h)} - {M (81h), M (80h)}

add:

MOVFW 80h

ADDWF 82h, 1

MOVFW 81h

ADDWFC83h, 1

sub:

MOVFW 80h

SUBWF 82h, 1

MOVFW 81h

SUBWFC 83h, 1

11.1.4.3

Interrupt Flag INTF and Interrupt enable register INTE

The interrupt enable register (INTE) records individual interrupt request .When Interrupt event occur and

Interrupt enable bit =1 , the interrupt flag will be set。The global interrupt enable bit (GIE) will enable CPU

interrupt procedure. When GIE=1 and any interrupt flag is set, CPU interrupt procedure would be executed.

CPU interrupt procedure executes GIE reset and CALL 0004h.

Note. When interrupt signal happened within Instruction Duty Cycle, the CPU must wait and till Instruction Duty

Cycle end of this program then produce an “Interrupt Flag” before go into next step.

11.1.5 Instruction Set

Instruction

Operation

Cylce

Flag

NOP

No operation

1

None

CLRF f

f=0

1

Z

ADDWF f, d

d=f+W

1

C, Z

INCF f, d

d=f+1

1

Z

INCFSZ f, d

d=f+1 skip if d=0

1,2

None

DECF f, d

d=f-1

1

Z

DECFSZ f, d

d=f-1 skip if d=0

1,2

None

SUBWF f, d

d=f-W

1

C, Z

COMF f, d

d=~f

1

Z

MOVWF f

f=W

1

None

MOVFW f

W=f

1

None

ADDWFC f, d

d=f+W+C

1

C, Z

ANDWF f, d

d=f&W

1

Z

IORWF f, d

d=f|W

1

Z

XORWF f, d

d=f^W

1

Z

RLF f, d

C, d [7:0]=f [7:0], C

1

C

SUBWFC f, d

d=f-W- (~C)

1

C, Z

RRF f, d

d [7:0], c=C, f [7:0]

1

C

ADDLW k

W=k+W

1

C, Z

SUBLW k

W=k-W

1

C, Z

ANDLW k

W=k&W

1

Z

IORLW k

W=k|W

1

Z

XORLW k

W=k^W

1

Z

MOVLW k

W=k

1

None

RETLW k

RETURN and W=k

2

None

CALL k

Push PC+1 and GOTO k

2

None

GOTO k

PC=k

2

None

RETFIE

Pop PC and GIE=1

2

None

RETURN

Pop PC

2

None