PCF8813 datasheet(42/72 Pages) PHILIPS

42 / 72 page

2004 Mar 05

Philips Semiconductors

Product speciﬁcation

(67 + 1)

× 102 pixels matrix LCD driver

PCF8813

Notes

1. fframe =

: (n depends on the multiplex rate, see Table 18).

2. VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C, all MUX settings.

3. VDD1 = 2.4 V to 3.0 V; Tamb = −20 °C to +70 °C; MUX = 68.

4. RES may be LOW before VDD on.

5. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit

board.

6. SDOUT disable time for SPI 3-line or 4-line interface.

7. SDOUT disable time for serial 3-line interface.

8. Typical conditions: VDD1 = 2.8 V, Tamb =20 °C, MUX = 68; fframe =70 ± 3.4 Hz.

9. Inputs SDAH and SCLH are filtered and will reject spikes on the bus lines with a width of less than tSW(max).

tHD;DAT

data hold time

−

tSU;STO

set-up time for STOP condition

160

−−

capacitive load for SDAH and

SCLH lines

total capacitance of one

bus line

−−

100

capacitive load for SDAH + SDA

line and SCLH + SCL line

−−

400

tSP

tolerable spike width on bus

note 9

−−

5ns

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

ext

-------

Table 18 Value of n as a function of multiplex rate

MULTIPLEX RATE

483

462

464

500

504

476

468

505

500

PCF8813 Datasheet(PDF) 42 Page - NXP Semiconductors

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