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NT5CC64M16GP-DHT Datasheet(PDF) 3 Page - Nanya Technology Corporation. |
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NT5CC64M16GP-DHT Datasheet(HTML) 3 Page - Nanya Technology Corporation. |
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3 / 160 page ![]() Version 2.2 3 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Descriptions The 1Gb Double-Data-Rate-3 (DDR3(L)) G-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/ pin/sec for general applications. The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067/+0.1V power supply and are available in BGA packages. |
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