NT5CC64M16GP-DHT datasheet(48/160 Pages) NANYA

48 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

READ Operation

Read Burst Operation

During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or

WRITE (AUTO PRECHARGE can be enabled or disabled).

A12=0, BC4 (BC4 = burst chop, tCCD=4)

A12=1, BL8

A12 is used only for burst length control, not as a column address.

Read Burst Operation RL=5 (AL=0, CL=5, BL=8)

Notes:

1. BL8, RL = 5, AL = 0, CL = 5.

2. DOUT n = data-out from column n.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.

READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)

Notes:

1. BL8, RL = 9, AL = (CL - 1), CL = 5.

2. DOUT n = data-out from column n.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.

CL=5

DQS, DQS

T10

READ

NOP

CMD

NOP

Bank

Col n

Address

Dout

n +1

Dout

n +2

Dout

n +3

Dout

n +4

Dout

n +5

Dout

n +6

Dout

n +7

RL = AL + CL

tRPRE

tRPST

CL=5

DQS, DQS

T10

READ

NOP

CMD

NOP

Bank

Col n

Address

Dout

n +1

Dout

n +2

Dout

n +3

RL = AL + CL

tRPRE

AL = 4

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