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NT5CB128M8GP-DHT Datasheet(PDF) 1 Page - Nanya Technology Corporation. |
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NT5CB128M8GP-DHT Datasheet(HTML) 1 Page - Nanya Technology Corporation. |
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1 / 160 page ![]() Version 2.2 1 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP NOTE 1 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand. NOTE 2 Please refer to ordering information for the detail. NOTE 3 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. Please refer to page 5 operating frequency table. 1.35V DDR3L-RS parts are exceptional and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts. NOTE 4 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled. NOTE 5 Violating tRFC specification will induce malfunction. NOTE 6 Only Support prime DQ ’s feedback for each byte lane. Please contact with NTC for the feedback of all DQs which is enabled by using an electrical fuse. Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/ ) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode CAS Latency (6/7/8/9/10/11/13/14) CAS Write Latency (5/6/7/8/9/10) Additive Latency (0/CL-1/CL-2) Write Recovery Time (5/6/7/8/10/12/14/16) Burst Type (Sequential/Interleaved) Burst Length (BL8/BC4/BC4 or 8 on the fly) Programmable Functions Self RefreshTemperature Range(Normal/Extended) Output Driver Impedance (34/40) On-Die Termination of Rtt_Nom(20/30/40/60/120) On-Die Termination of Rtt_WR(60/120) Precharge Power Down (slow/fast) Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) Signal Synchronization - Write Leveling via MR settings 6 - Read Leveling via MPR Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1353 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V) Features Density and Addressing Organization 128Mb x 8 64Mb x 16 Bank Address BA0 – BA2 BA0 – BA2 Auto precharge A10 / AP A10 / AP BL switch on the fly A12 / A12 / Row Address A0 – A13 A0 – A12 Column Address A0 – A9 A0 – A9 Page Size 1KB 2KB tREFI(us) 4 Tc<=85℃:7.8, Tc>85℃:3.9 tRFC(ns) 5 110 Packages / Density Information Lead-free RoHS compliance and Halogen-free 1Gb Length x Width Ball pitch (Org. / Package) (mm) (mm) 128Mbx8 78-ball VFBGA 8.00 x 10.50 0.80 64Mbx16 96-ball VFBGA 8.00 x 13.00 0.80 Speed Grade (CL-TRCD-TRP) 2 - 2133 Mbps / 14-14-14 - 1866 Mbps / 13-13-13 - 1600 Mbps / 11-11-11, 10-10-10 Temperature Range (Tc) 4 - Commercial Grade = 0℃~95℃ - Quasi Industrial Grade (-T) = -40℃~95℃ - Industrial Grade (-I) = -40℃~95℃ - Automotive Grade 2 (-H) = -40℃~105℃ - Automotive Grade 3 (-A) = -40℃~95℃ Options NTC has the rights to change any specifications or product without notification. |
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