NT5CB128M8GP-EKB datasheet(126/160 Pages) NANYA

126 / 160 page

Version 2.2

126

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

IDD3P

Active Power-Down Current

CKE: Low; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0

IDD4R

Operating Burst Read Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1,7); AL: 0;

: High between RD;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: seamless read data burst with different data between one burst and the next one;

DM:stable at 0;

Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

IDD4W

Operating Burst Write Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: High between WR;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: seamless write data burst with different data between one burst and the next one ;

DM: stable at 0;

Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at HIGH;

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