NT5CC128M8GP-EKB datasheet(65/160 Pages) NANYA

65 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command).

CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down

exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet.

Active Power-Down Entry and Exit timing diagram

Ta0

Ta1

Tb0

Tb1

Tc0

Valid

NOP

CMD

CKE

Valid

tIS

tIH

tPD

tIH

tIS

tCKE

Address

Valid

tCPDED

Enter

Power-Down

Exit

Power-Down

tXP

Do not

care

Time

Break

Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate,

Precharge, Refresh, MRS:

Power-Down Entry after Read and Read with Auto Precharge

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

RD or

RDA

NOP

CMD

CKE

Address

Valid

Power-Down

Entry

Do not

care

Time

Break

Ta6

Ta7

Ta8

Tb0

Tb1

NOP

Valid

tIS

tCPDED

RL = AL + CL

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

Din

b+1

Din

b+2

Din

b+3

tRDPDEN

BL8

BC4

tPD

DQS,

DQS

NT5CC128M8GP-EKB Datasheet(PDF) 65 Page - Nanya Technology Corporation.

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