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NT5CC128M8GP-EKB Datasheet(PDF) 75 Page - Nanya Technology Corporation.

Part # NT5CC128M8GP-EKB
Description  Commercial, Industrial and AutomotiveDDR3(L) 1 Gb SDRAM
PDF  160 Pages
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Manufacturer  NANYA [Nanya Technology Corporation.]
Direct Link  http://www.nanya.com
Logo NANYA - Nanya Technology Corporation.

NT5CC128M8GP-EKB Datasheet(HTML) 75 Page - Nanya Technology Corporation.

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Version 2.2
75
Nanya Technology Cooperation ©
04/2019
All Rights Reserved.
NTC Proprietary
Level: Property
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8GN / NT5CB(C)64M16GP
Latencies and timing parameters relevant for Dynamic ODT
Name and Description
Abbr.
Defined from
Defined to
Definition for all
DDR3(L) speed pin
Unit
ODT turn-on Latency
ODTLon
registering external
ODT signal high
turning termination on
ODTLon=WL-2
tCK
ODT turn-off Latency
ODTLoff
registering external
ODT signal low
turning termination off
ODTLoff=WL-2
tCK
ODT Latency for changing from
RTT_Nom to RTT_WR
ODTLcnw
registering external
write command
change RTT strength from
RTT_Nom to RTT_WR
ODTLcnw=WL-2
tCK
ODT Latency for change from
RTT_WR to RTT_Nom (BL=4)
ODTLcwn4
registering external
write command
change RTT strength from
RTT_WR to RTT_Nom
ODTLcwn4=4+ODTLoff
tCK
ODT Latency for change from
RTT_WR to RTT_Nom (BL=8)
ODTLcwn8
registering external
write command
change RTT strength from
RTT_WR to RTT_Nom
ODTLcwn8=6+ODTLoff
tCK(avg)
Minimum ODT high time
after ODT assertion
ODTH4
registering ODT high
ODT registered low
ODTH4=4
tCK(avg)
Minimum ODT high time
after Write (BL=4)
ODTH4
registering write with
ODT high
ODT registered low
ODTH4=4
tCK(avg)
Minimum ODT high time
after Write (BL=8)
ODTH8
registering write with
ODT high
ODT register low
ODTH8=6
tCK(avg)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
tCK(avg)
Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)



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