NT5CC128M8GP-EKB datasheet(125/160 Pages) NANYA

125 / 160 page

Version 2.2

125

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Pecharge Power Down Mode: Slow Exit(3)

IDD2P(1)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Pecharge Power Down Mode: Fast Exit(3)

IDD2Q

Precharge Quiet Standby Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0

IDD3N

Active Standby Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: MID-LEVEL;

DM:stable at 0;

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