SC2599

5

Block Diagram

DRIV E R

L OGIC

VIN

2

VTT

3

GND

4

VD D

1

UV L O

S o ft-S ta rt

EN

5

VTTS

6

V DDQ

8

+

-

VR EF

7

EN \

R

R

T herm a l

S hutdow n

Pin #

Pin Name

Pin Function

1

VDD

Input bias voltage — 2.35V to 3.6V . Connect a ceramic capacitor from this pin to GND.

2

VIN

LDO input range — 1V to 3.6V. Connect ceramic capacitors from this pin to GND.

3

VTT

Output of the linear regulator. Connect ceramic capacitors from this pin to GND.

4

GND

Ground reference for the IC.

5EN

Logic input to enable or disable the VTT output. If EN pin is grounded to shut down the linear regulator,

VREF remains active.

6

VTTS

VTT output sense input. Connect VTTS to the output at the output capacitor to implement remote sense.

7

VREF

The reference output, equal to one half of VDDQ. Connect a 100nF capacitor from this pin to GND.

8

VDDQ

External reference input; range 1V to 3.6V.

PAD

GND

Thermal pad. This pad must be connected to GND. For optimal heat sinking, connect to the GND plane us-

ing multiple vias.

Pin Descriptions