PCI6621 datasheet(68/204 Pages) TI

68 / 204 page

3−20

PCI Bus

PCI6x21/

PCI6x11

EEPROM

Power Switch

SD/MMC

Card/

UltraMedia

Card

Power

Switch

Card/

UltraMedia

Card

Power Switch

SD/MMC

MS/MSPRO

SM/xD

† The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI6x21/PCI6x11 controller. PRST

must be asserted for subsequent warm resets.

Figure 3−12. System Diagram Implementing CardBus Device Class Power Management

3.8.1

Integrated Low-Dropout Voltage Regulator (LDO-VR)

The PCI6x21/PCI6x11 controller requires 1.5-V core voltage. The core power can be supplied by the

PCI6x21/PCI6x11 controller itself using the internal LDO-VR. The core power can alternatively be supplied by an

external power supply through the VR_PORT terminal. Table 3−13 lists the requirements for both the internal core

power supply and the external core power supply.

Table 3−13. Requirements for Internal/External 1.5-V Core Power Supply

SUPPLY

VCC

VR_EN

VR_PORT

NOTE

Internal

3.3 V

GND

1.5-V output

Internal 1.5-V LDO-VR is enabled. A 1.0-

µF bypass capacitor is required on the VR_PORT

terminal for decoupling. This output is not for external use.

External

3.3 V

VCC

1.5-V input

Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA

capacity, is required. A 0.1-

µF bypass capacitor on the VR_PORT terminal is required.

3.8.2

CardBus (Functions 0 and 1) Clock Run Protocol

The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI6x21/PCI6x11

controller. CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement

CLKRUN, this is not always available to the system designer, and alternate power-saving features are provided. For

details on the CLKRUN protocol see the PCI Mobile Design Guide.

The PCI6x21/PCI6x11 controller does not permit the central resource to stop the PCI clock under any of the following

conditions:

•

Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.

•

The 16-bit PC Card resource manager is busy.

•

The PCI6x21/PCI6x11 CardBus master state machine is busy. A cycle may be in progress on CardBus.

PCI6621 Datasheet(PDF) 68 Page - Texas Instruments

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