PCI6621 datasheet(91/204 Pages) TI

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4−15

Table 4−6. Interrupt Pin Register Cross Reference

INTRTIE BIT

(BIT 29,

OFFSET 80h)

TIEALL BIT

(BIT 28,

OFFSET 80h)

INTPIN

FUNCTION 0

(CARDBUS)

INTPIN

FUNCTION 1

(CARDBUS)

INTPIN

FUNCTION 3

(FLASH MEDIA)

INTPIN

Function 4

(SD Host)

INTPIN

Function 5

(Smart Card)

01h (INTA)

02h (INTB)

Determined by bits

6−5 (INT_SEL field) in

flash media general

Determined by bits

6−5 (INT_SEL field) in

SD host general

Determined by bits

6−5 (INT_SEL field) in

Smart Card general

01h (INTA)

flash media general

control register (see

Section 7.21)

SD host general

control register (see

Section 8.22)

Smart Card general

control register (see

Section 9.22)

01h (INTA)

0x01 (INTA)

4.25 Bridge Control Register

The bridge control register provides control over various PCI6x21/PCI6x11 bridging functions. Some bits in this

of the register contents.

Bit

Name

Bridge control

Type

Default

Bridge control

Offset:

3Eh (Function 0, 1)

Type:

Read-only, Read/Write

Default:

0340h

Table 4−7. Bridge Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

15−11

RSVD

These bits return 0s when read.

POSTEN

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables the

posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst

cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket

dependent and is not shared between functions 0 and 1.

PREFETCH1

Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is

socket dependent. This bit is encoded as:

0 = Memory window 1 is nonprefetchable.

1 = Memory window 1 is prefetchable (default).

PREFETCH0

Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is

socket dependent. This bit is encoded as:

0 = Memory window 0 is nonprefetchable.

1 = Memory window 0 is prefetchable (default).

INTR

PCI interrupt − IREQ routing enable. This bit is used to select whether PC Card functional interrupts are

routed to PCI interrupts or to the IRQ specified in the ExCA registers.

0 = Functional interrupts are routed to PCI interrupts (default).

1 = Functional interrupts are routed by ExCA registers.

6 †

CRST

CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST

signal can also be asserted by passing a PRST assertion to CardBus.

0 = CRST is deasserted.

1 = CRST is asserted (default).

This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.

† One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not

enabled, then this bit is cleared by the assertion of PRST or GRST.

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