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XRT75VL00D Datasheet(PDF) 18 Page - Exar Corporation |
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XRT75VL00D Datasheet(HTML) 18 Page - Exar Corporation |
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18 / 92 page ![]() XRT75VL00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 13 JITTER ATTENUATOR INTERFACE PIN #SIGNAL NAME TYPE DESCRIPTION 6 JA0 I Disable Jitter Attenuator/FIFO Size Select:: In Hardware Mode, this pin along with JA1 pin provides the following functions in the table below. NOTE: This pin is internally pulled down. 7 JA1 I Disable Jitter Attenuator/FIFO Size Select: In Hardware Mode, this pin along with JA0 pin provides the functions in the table above. NOTE: This pin is internally pulled down. 8 JA Tx/Rx I Jitter Attenuator Select: In Hardware Mode setting this pin “High” selects the Jitter Attenuator in the Transmit path and setting “Low” selects in Receive path. NOTE: This pin is internally pulled down. JA0 0 0 Operation 16 bit FIFO 32 bit FIFO JA1 0 1 1 1 128 bit FIFO Disable Jitter Attenuator 0 1 |
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