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AN2629 Datasheet(PDF) 18 Page - STMicroelectronics |
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AN2629 Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 43 page  Real-time clock (RTC) AN2629 18/43 Doc ID 13922 Rev 2 3.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset. Refer to the STM32F10xxx reference manual. 3.3.3 Reading RTC registers The RTC core is completely independent from the RTC APB1 interface. Software accesses the RTC prescaler, counter and alarm values through the APB1 interface but the associated readable registers are internally updated at each rising edge of the RTC clock resynchronized by the RTC APB1 clock. This is also true for the RTC flags. This means that the first read to the RTC APB1 registers may be corrupted (generally read as 0) if the APB1 interface has previously been disabled and the read occurs immediately after the APB1 interface is enabled but before the first internal update of the registers. This can occur if: ● A system reset or power reset has occurred ● The MCU has just woken up from Standby mode (see the STM32F10xxx reference manual) ● The MCU has just woken up from Stop mode (see the STM32F10xxx reference manual) In all the above cases, the RTC core has been kept running while the APB1 interface was disabled (reset, not clocked or not powered). Consequently when reading the RTC registers, after having disabled the RTC APB1 interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the RTC_CRL register to be set by hardware. Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes. 3.3.4 Configuring RTC registers To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register. In addition, writing to any RTC register is only enabled if the previous write operation is finished. To enable the software to detect this situation, the RTOFF status bit is provided in the RTC_CR register to indicate that an update of the registers is in progress. A new value can be written to the RTC registers only when the RTOFF status bit value is ‘1’. Configuration procedure: 1. Poll RTOFF, wait until its value goes to ‘1’ 2. Set the CNF bit to enter configuration mode 3. Write to one or more RTC registers 4. Clear the CNF bit to exit configuration mode 5. Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation. The write operation only executes when the CNF bit is cleared; it takes at least three RTCCLK cycles to complete. |
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