LMX9820ASM datasheet(35/44 Pages) NSC

35 / 44 page

Revision 1.0

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14.0 Application Information (Continued)

14.0 Application Information

Figure 22 on page 35 represents a typical system sche-

matic for the LMX9820A.

14.1 MATCHING NETWORK

The antenna matching network may or may not be

required, depending upon the impedance of the antenna

chosen. A 6.8 pF blocking capacitor is recommended.

14.2 FILTERED POWER SUPPLY

It is important to provide the LMX9820A with adequate

ground planes and a filtered power supply. It is highly rec-

ommended that a 0.1 µF and a 10 pF bypass capacitor be

placed as close as possible to VCC (pad H2) on the

LMX9820A.

14.3 HOST INTERFACE

To set the logic thresholds of the LMX9820A to match the

host system, IOVCC (pad H12) must be connected to the

logic power supply of the host system. It is highly recom-

mended that a 10 pF bypass capacitor be placed as close

as possible to the IOVCC pad on the LMX9820A.

ISEL2 (pad H13) and ISEL1 (pad J13) can be strapped to

the host logic 0 and 1 levels to set the host interface boot-

up configuration. Alternatively both ISEL2 and ISEL1 can

be hardwired over 10k

Ω pullup/pulldown resistors.

Env0 (pad E9) and Env1 (pad B11) can be left uncon-

nected (both are pulled high), if no ISP capability is

required. If the ISP environment mode is needed, then

Env0 must be driven to logic low and Reset needs to be

asserted. After de-assertion of Reset, the LMX9820A boots

into the mode corresponding to the values present on Env0

and Env1. Alternatively, a firmware upgrade command can

be used.

14.4 CLOCK INPUT

The clock source must be placed as close as possible to

the LMX9820A. The quality of the radio performance is

directly related to the quality of the clock source connected

to the oscillator port on the LMX9820A. Careful attention

must be paid to the crystal/oscillator parameters or radio

performance could be drastically reduced.

14.5 SCHEMATIC AND LAYOUT EXAMPLES

Notes:

Capacitor values, Ct1 and Ct2 may vary depending on board design crystal manufacturer specification.

Single ground plane is used for both RF and digital grounds.

Figure 22. Example System Schematic

B1 Antenna

RF_inout

Clk+

Clk-

12 MHz

Ct1

Ct2

VCC

10 pF

0.01 µF

10 pF

0.01 µF

H12

IOVCC

Reset_b

Reset_5100

Env0

Env1

Uart_rx

Uart_tx

Uart_cts

Uart_rts

D11

B11

D10

C10

RF GND

Dig_gnd[1:2]

LMX9820A

D12, G11

Reference

Table 18 on

page 15.

Reference

Table 17 on

page 15.

Reference Table

25 on page 23

for correct POR

timing.

Connect to

system

UART bus.

No HW Flowcontrol:

- CTS GND

- RTS NC

ISEL2

ISEL1

H13

J13

6.8 pF

AAI_srd

AAI_std

AAI_sfs

AAI_sclk

Connect

PCM

codec

or leave open

32kHz_CLKI

max

Ω

VCC

B13

B10

B12

C11

C12

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