2 Channel 5.5V 1.5A 1.5MHz DC-DC Step down PMU

and temperature. The minimum recommended value for the input capacitor is 10µF with an ESR of 10mΩ or less.

The input capacitors need to be mounted as close as possible to the power/ground input terminals of the device.

The input power source supplies the average current continuously. During the high side MOSFET switch on-time,

however, the demanded di/dt is higher than can be typically supplied by the input power source. This delta is

supplied by the input capacitor.

A simplified “worst case” assumption is that all of the high side MOSFET current is supplied by the input capacitor.

This will result in conservative estimates of input ripple voltage and capacitor RMS current.

Input ripple voltage is estimated as follows:

where

•

: Estimated peak-to-peak input ripple voltage

•

: Output current

•

: Input capacitor value

•

: Input capacitor ESR

This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS

current rating. Capacitor RMS current estimated as follows:

2

+

2

12

)

Where

RMSCIN

: Estimated input capacitor RMS current

Layout Guidelines

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of

a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in

the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good

layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched

rapidly. The first loop starts from the CIN input capacitor, to the regulator VIN terminal, to the regulator SW terminal,

to the inductor then out to the output capacitor COUT and load. The second loop starts from the output capacitor

ground, to the regulator GND terminals, to the inductor and then out to COUT and the load. To minimize both loop

areas the input capacitor should be placed as close as possible to the VIN terminal. Grounding for both the input and

output capacitors should consist of a small localized top side plane that connects to GND. The inductor should be

placed as close as possible to the SW pin and output capacitor.

2. Minimize the copper area of the switch node. The SW terminals should be directly connected with a trace that

runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible and with a

sufficient width. However, a trace that is wider than 100 mils will increase the copper area and cause too much

capacitive loading on the SW terminal. The inductors should be placed as close as possible to the SW terminals to

further minimize the copper area of the switch node.

3. Have a single point ground for all device analog grounds. The ground connections for the feedback components

should be connected together then routed to the GND pin of the device. This prevents any switched or load currents

from flowing in the analog ground plane. If not properly handled, poor grounding can result in degraded load

regulation or erratic switching behavior.

4. Minimize trace length to the FB terminal. The feedback trace should be routed away from the SW pin and inductor

to avoid contaminating the feedback signal with switch noise.

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output

of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage

sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy.

HM5213