ASM3P2508A datasheet(8/11 Pages) ALSC

8 / 11 page

Peak EMI Reducing Solution

8 of 11

rev 1.3

February 2005

ASM3P2508A

An example of a Byte Write via I2C to partially ‘power

down’ the device:

ASM3P2508A can be partially ‘powered down’ using bit 1

of Byte 0. The organization of the register bits for Byte ‘0’ is

given with default values below:

Bit

Resv Resv Resv Resv Resv Resv

PLL2

Enable

PLL1

Enable

The function of partial power down of the device is of

interest to us - that is bit 1 of Byte 0. In the default mode

this bit is logic ‘1’. As such, the Byte 0 default value is

57 (H). To put ASM3P2508A in ‘power down’ mode, the

bit 1 of Byte 0 is to be changed to logic ‘0’. Hence writing a

55 (H) via I2C into Byte 0 would put the device in partial

‘power down’ mode where the PLL block generating

72 MHz / 48 MHz would be powered down while I2C block,

crystal oscillator, and the PLL block generating 120 MHz

would still be active. The organization of the register bits is

as below:

Bit

Resv

PLL2

Enable

PLL1

Enable

Byte 0

Byte 1

FOUT1CLK (MHz)

FOUT2CLK(MHz)

Power up default

6F(H)

3F(H)

120

48_MHz Mode

6F(H)

BF(H)

120

Power down PLL with 72MHz

6D(H)

3F(H)

120

Power down PLL with 48MHz

6D(H)

BF(H)

120

Figure showing a complete data transfer:

ASM3P2508A Datasheet(PDF) 8 Page - Alliance Semiconductor Corporation

ASM3P2508A Datasheet(HTML) 8 Page - Alliance Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11

Datasheet Download

Link URL