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ASM3P2508A Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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ASM3P2508A Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 11 page ![]() Alliance Semiconductor 2575 Augustine Drive • Santa Clara CA • Tel: 408-855-4900 • Fax: 408-855-4999 • www.alsc.com rev 1.3 February 2005 ASM3P2508A Peak EMI Reducing Solution Features Generates an EMI optimized clocking signal at output. Input frequency – 14.31818 MHz. Frequency outputs: o 120 MHz (modulated) - default. o 72 MHz (modulated) or 48 MHz (modulated) selectable via I2C ± 1% Centre spread. Modulation rate: 40 KHz. Byte Write via I2C Supply voltage range 3.3V ± 0.3V. Available in 8-pin SOIC Package. Available in Commercial and Industrial Temperature ranges. Product Description The ASM3P2508A is a versatile spread spectrum frequency modulator. The ASM3P2508A reduces electromagnetic interference (EMI) at the clock source. The ASM3P2508A allows significant system cost savings by reducing the number of circuit board layers and shielding that are required to pass EMI regulations. The ASM3P2508A modulates the output of PLL in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most clock generators. Lowering EMI by increasing a signal’s bandwidth is called spread spectrum clock generation. The ASM3P2508A has a feature to power down the 72MHz/48MHz output by writing data into specific registers in the device via I2C. By writing a ‘0’ into bit 1 of Byte 0, the PLL block generating 72 MHz / 48MHz can be powered down. Writing ‘0’ into bit ‘7’ of Byte 1 selects an output of 72 MHz on FOUT2CLK while a ‘1’ at the same location selects a 48 MHz clock output. However, the I2C block, crystal oscillator, and the PLL block generating 120MHz would be always running. Block Diagram FOUT2CLK (72 MHz / 48 MHz) SDA Crystal Oscillator PLL 1 SCL XIN XOUT VSS VDD FOUT1CLK (120 MHz) I2C Interface PLL 2 |
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