PDP83TG720SWCSTQ1 datasheet(36/199 Pages) TI

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TX_CTRL

TX_D3

TX_D2

TX_D1 / TX_P

TX_D0 / TX_M

VDDIO

LED_0 / GPIO_0

MDIO

INH

VDDA

TRD_P

TRD_M

STRAP_1

RX_CTRL

CLKOUT / GPIO_2

DNC

GND

DNC

TX_CLK

Power Management

Module

Enable

GND

VDDIO

VDD1P0

VDDA

Vsleep source = 3.3V;

Always on : Sleep or Functional mode

Enable = 0 -> VDDIO, VDD1P0, VDDA -> Powered

Enable = 1 -> VDDIO, VDD1P0, VDDA -> Powered

Sleep mode -> INH = 0

Out of sleep -> INH = 1 (3.3V)

Figure 7-13. Required Implementation for Sleep Mode

Note

Phy will not go into sleep mode if supply sources are not disabled as per above figure.

7.4.6 State Transitions

7.4.6.1 State Transition #1 - Standby to Normal

Autonomous Operation: The PHY will automatically transition to Normal state upon POR completion.

Managed Operation: The PHY will transition to Normal state out of Standby only after writing register <0x018C>

= 0x001.

7.4.6.2 State Transition #2 - Normal to Standby

The PHY can be forced back into Standby when in Normal state by writing register <0x018C> = 0x0010.

7.4.6.3 State Transition #3 - Normal to Sleep

Sleep state can be entered either locally (pin/register-write) or by remote link-partner.

Local sleep entry for Master mode phy :

• Step 1 : Write bit[7] = 'b1 of register[0x0182].

• Step 2 : Make "wake" pin low.

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

www.ti.com

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PDP83TG720SWCSTQ1 Datasheet(PDF) 36 Page - Texas Instruments

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