VT6307 datasheet(33/54 Pages) VIA

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VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

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Interrupt Registers

Memory Offset 80 (Set), 84 (Clear) – Interrupt Events RW

31-27 Reserved

........................................ always reads 0

PHY Register Data Received

PHY register data byte received (data byte not sent

when register 0 received)

Cycle Too Long

More than 115 usec (but not more than 120 usec)

elapsed between the start of sending a cycle start

packet and the end of a subaction gap.

Unrecoverable Error

Error encountered that has forced the chip to stop

operations of any or all subunits (e.g., when a DMA

context sets its “ContextControl.Dead” bit)

Cycle Inconsistent

Cycle start received with a cycle count different from

the value in the “Cycle Timer” register

Cycle Lost

Expected cycle start not received (cycle start not

received immediately after the first subaction gap

after the “Cycle Sync” event or arbitration reset gap

detected after a “Cycle Sync” event without an

intervening cycle start).

Cycle 64 Seconds Interrupt

Bit 7 of the “Cycle Seconds Counter” has changed.

Cycle Synch Interrupt

New isochronous cycle started (least significant bit of

the cycle count toggled).

PHY Requested Interrupt

The PHY has requested an interrupt using a status

transfer.

Reserved

........................................ always reads 0

Bus Reset Entered

The Phy has entered bus reset mode.

Self-ID Complete

Self-ID packet stream received.

15-10 Reserved

........................................ always reads 0

Lock Response Error

Lock response sent to a serial bus register in response

to a lock request but no “ack_complete” received.

Posted Write Error

A host bus error occurred while the chip was trying to

write a 1394 write request (which had already been

given an “ack_complete”) into system memory.

Isochronous ReceiveDMA Complete

One or more Isochronous receive contexts have

generated an interrupt (one or more bits have been set

in the “Isochronous Receive Interrupt Event” register

masked by the “Isochronous Receive Interrupt Mask”

Isochronous Transmit DMA Complete

One or more Isochronous transmit contexts have

generated an interrupt (one or more bits have been set

in the

“Isochronous

Transmit Interrupt Event”

masked

by the

“Isochronous

Transmit

Interrupt Mask” register).

Response Packet Sent

A packet was sent to an asynchronous receive

response context buffer.

Receive Packet Sent

A packet was sent to an asynchronous receive request

context buffer.

Async Receive Response DMA Complete

Conditionally set upon completion of an ARDMA

Response context command descriptor.

Async Receive Request DMA Complete

Conditionally set upon completion of an ARDMA

Request context command descriptor.

Async Response Transmit DMA Complete

Conditionally set upon completion of an ATDMA

Response command.

Async Request Transmit DMA Complete

Conditionally set upon completion of an ATDMA

Request command.

Memory Offset 88 (Set), 8C (Clear) – Interrupt Mask.. RW

The bits in this register (except for the Master Interrupt Enable

bit in bit-31) correspond to the bits in the Interrupt Event

interrupt condition from generating an interrupt. Bits are set in

the mask register by writing one bits to the “Set” address and

cleared by writing one bits to the “Clear” address. The current

value of the mask bits may be read from either address.

Master Interrupt Enable

Disable All Interrupt Events................... default

Generate interrupts per mask bits 0-26

30-27 Reserved

........................................always reads 0

26-0 Interrupt Mask ........................... default = undefined

(see Interrupt Event register)

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