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STM32WB55CCU6TR Datasheet(PDF) 72 Page - STMicroelectronics |
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STM32WB55CCU6TR Datasheet(HTML) 72 Page - STMicroelectronics |
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72 / 193 page ![]() Pinouts and pin description STM32WB55xx STM32WB35xx 72/193 DS11929 Rev 10 41 PA14 (JTCK-SWCLK) I/O FT (8) JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA, SAI1_FS_B, CM4_EVENTOUT - 42 PA15 (JTDI) I/O FT (8) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, CM4_EVENTOUT, MCO - 43 PB3 (JTDO) I/O FT_a - JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, USART1_RTS_DE, SAI1_SCK_B, CM4_EVENTOUT COMP2_INM 44 PB4 (NJTRST) I/O FT_fa (8) NJTRST, I2C3_SDA, SPI1_MISO, USART1_CTS, SAI1_MCLK_B, TIM17_BKIN, CM4_EVENTOUT COMP2_INP 45 PB5 I/O FT_a - LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, LPUART1_TX, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, CM4_EVENTOUT - 46 PB6 I/O FT_fa - LPTIM1_ETR, I2C1_SCL, USART1_TX, SAI1_FS_B, TIM16_CH1N, MCO, CM4_EVENTOUT COMP2_INP 47 PB7 I/O FT_fa - LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, TIM17_CH1N, CM4_EVENTOUT COMP2_INM, PVD_IN 48 VDD S - - - - 1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the use of the PC14 and PC15 GPIOs in output mode is limited: - the speed must not exceed 2 MHz with a maximum load of 30 pF - these GPIOs must not be used as current sources (e.g. to drive a LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0434, available on www.st.com. 3. The clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes. 4. RF pin, use the nominal PCB layout. 5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165). 6. Reserved, must be kept unconnected. 7. High frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0 and 1) during RF operation. 8. After reset these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and PB4 pins and the internal pull-down on PA14 pin are activated. Table 17. STM32WB35xx pin and ball definitions (continued) Pin Alternate functions Additional functions Name (function after reset) |
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