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STM32WB55CCU6TR Datasheet(PDF) 33 Page - STMicroelectronics

Part # STM32WB55CCU6TR
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution
PDF  193 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB55CCU6TR Datasheet(HTML) 33 Page - STMicroelectronics

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DS11929 Rev 10
33/193
STM32WB55xx STM32WB35xx
Functional overview
57
The system clock after wakeup is 16 MHz, derived from the HSI16. If used, the SMPS
is restarted automatically.
In this mode the RF can be used.
Shutdown
The Shutdown mode allows to achieve the ultimate lowest power consumption. The
internal regulator is switched off so that the VCORE domain is powered off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is 4 MHz, derived from the MSI.
In this mode the RF is no longer operational.
When the RF subsystem is active, it changes the power state according to its needs (Run,
Stop, Standby). This operation is transparent for the CPU1 host application and managed by
a dedicated HW state machine. At any given time the effective power state reached is the
higher one needed by both the CPU1 and RF sub-system.
Table 7 summarizes the peripheral features over all available modes. Wakeup capability is
detailed in gray cells.
Table 7. Features over all modes(1)
Peripheral(2)
Stop0/Stop1
Stop 2
Standby Shutdown
-
-
-
-
CPU1
Y
-
Y
-
-
--
--
--
--
CPU2
Y
-
Y
-
-
--
--
--
--
Radio system
(BLE, 802.15.4)
YY(3)
Y-
-
Y
YY
YY(4) Y(4)
Flash memory
Y (5)
YO(6) O(6)
R
-R
-R
-R
-R
SRAM1
Y
Y(7)
YY(7)
R
-R
--
--
--
SRAM2a
Y
Y(7)
YY(7)
R
-R
-R(8)
--
--
SRAM2b
Y
Y(7)
YY(7)
R
-R
--
--
--
Quad-SPI
O
O
O
O
-
--
--
--
--
Backup registers
Y
Y
Y
Y
R
-R
-R
-R
-R
Brown-out reset (BOR)
Y
Y
Y
Y
Y
YY
YY
Y-
--



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