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7.10.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset

related signals.

Table 7-4. MCU_PORz Timing Requirements

see Figure 7-5

NO.

MIN

MAX UNIT

RST1

th(SUPPLIES_VALID - MCU_PORz)

Hold time, MCU_PORz active (low) at Power-up

after supplies valid (using external crystal)

9500000

RST2

Hold time, MCU_PORz active (low) at Power-up

after supplies valid and external clock stable (using

external LVCMOS oscillator)

1200

RST3

tw(MCU_PORzL)

Pulse Width minimum, MCU_PORz low after

Power-up (without removal of Power or system

reference clock MCU_OSC0_XI/XO)

1200

Figure 7-5. MCU_PORz Timing Requirements

Table 7-5. MCU_RESETSTATz, and RESETSTATz Switching Characteristics

see Figure 7-6

NO.

PARAMETER

MIN

MAX UNIT

RST4

td(MCU_PORzL-MCU_RESETSTATzL)

Delay time, MCU_PORz active (low) to

MCU_RESETSTATz active (low)

RST5

td(MCU_PORzH-MCU_RESETSTATzH)

Delay time, MCU_PORz inactive (high) to

MCU_RESETSTATz inactive (high)

6120*S(1)

RST6

td(MCU_PORzL-RESETSTATzL)

Delay time, MCU_PORz active (low) to

RESETSTATz active (low)

RST7

td(MCU_PORzH-RESETSTATzH)

Delay time, MCU_PORz active (low) to

RESETSTATz active (low)

9195*S(1)

RST8

tw(MCU_RESETSTATzL)

Pulse Width Minimum MCU_RESETSTATz low

(SW_MCU_WARMRST)

4040*S(1)

RST9

tw(RESETSTATzL)

Pulse Width Minimum RESETSTATz low

(SW_MCU_WARMRST, SW_MAIN_PORz, or

SW_MAIN_WARMRST)

301200

(1)

S = MCU_OSC0_XI/XO clock period

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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