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AM6421 Datasheet(PDF) 207 Page - Texas Instruments |
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AM6421 Datasheet(HTML) 207 Page - Texas Instruments |
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207 / 237 page ![]() Table 7-124. JTAG Timing Conditions (continued) PARAMETER MIN MAX UNIT CL Output load capacitance 5 15 pF Table 7-125. JTAG Timing Requirements see Figure 7-110 NO. MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 45.5 ns J2 tw(TCKH) Pulse width minimum, TCK high 18.2 ns J3 tw(TCKL) Pulse width minimum, TCK low 18.2 ns J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 4 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 4 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 2 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 2 ns Table 7-126. JTAG Switching Characteristics see Figure 7-110 NO. PARAMETER MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 14 ns TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 Figure 7-110. JTAG Timing Requirements and Switching Characteristics www.ti.com AM6442, AM6441, AM6421 AM6412, AM6411 SPRSP56 – JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 207 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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