LAN7431 datasheet(22/77 Pages) MICROCHIP

22 / 77 page

LAN7430/LAN7431

DS00002631D-page 22

 2018-2019 Microchip Technology Inc.

EEPROM Data In

/ Out

EEDIO

VIS / VO12

(PD)

This bidirectional pin is used for the EEPROM data. This

pin directly drives the data input of the external EEPROM.

The data output of the external EEPROM drives this pin

through an external resistor.

Note:

The internal pull-down holds a low on the pin

during reset and provides a low on the input if

an EEPROM is not connected.

Note:

An external resistor, on the EEPROM’s data

output, must be used to prevent contention

during data read operations.

EEPROM Clock

EECLK

VO12

(PD)

This pin drives the clock input of the external EEPROM.

Note:

The internal pull-down holds a low on the

output pin during reset.

Miscellaneous

General

Purpose I/O x

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

VIS/

VO8/

VOD8

(PU)

Each of these general purpose I/O pins is fully program-

mable as either a push-pull output, an open-drain output,

or a Schmitt-triggered input with pull-up.

Note:

The pull-up is only enabled if the pin is set as

a GPIO.

Note:

GPIO0

through GPIO3 are available for the

LAN7430 and LAN7431.

Note:

GPIO4

through GPIO11 are available only for

the LAN7431.

Test Pin

TEST

VIS

(PD)

This pin is used to enable test modes and must be con-

nected to ground for proper functional operation.

System Reset

RESET_N

VIS

System reset. This pin is active low.

Note:

If this signal is unused it must be pulled up to

VDDVARIO.

Indicator LEDs

LED0

LED1

LED2

LED3

VOD12

VOS12

(LAN7430 only)

LED signal sourced from Gigabit Ethernet PHY.

Note:

When enabled as LED outputs, the pins are

either open-Drain or open-Source drivers.

External PHY Bias

Resistor

ISET

This pin should be connect to ground through a 6.04K 1%

resistor.

JTAG

JTAG Test Mux

Select

TMS

VIS

JTAG test mode select.

JTAG Test Clock

TCK

VIS

JTAG test clock.

Note:

The maximum operating frequency of this clock

is half of the system clock.

JTAG Test Data

Input

TDI

VIS

JTAG data input

JTAG Test Data

Output

TDO

VO12

JTAG data output.

TABLE 3-3:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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