LAN7431 datasheet(61/77 Pages) MICROCHIP

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DS00002631D-page 61

LAN7430/LAN7431

7.6.6

RGMII TIMING (LAN7431 ONLY)

This section specifies the LAN7431 RGMII interface transmit and receive timing. The RGMII interface supports the inde-

pendent enabling/disabling of the TXC and RXC delays, each with unique timing properties. The RGMII timing with the

TXC/RXC delays enabled/disabled are detailed in the following sub-sections.

7.6.6.1

RGMII Transmit Timing (TXC Internal Delay Enabled - MAC Provides Delayed Clock)

Note 7-20

7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.

Minimum limits are non-sustainable long term.

Note 7-21

8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.

Note 7-22

8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.

Maximum limits are non-sustainable long term.

Note 7-23

45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.

Note 7-24

55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.

Note:

All RGMII timing specifications assume a point-to-point test circuit as defined in Figure 3 of the RGMII spec-

ification 2.0.

FIGURE 7-8:

RGMII TRANSMIT TIMING (TXC INTERNAL DELAY ENABLED)

TABLE 7-16:

RGMII TRANSMIT TIMING VALUES (TXC INTERNAL DELAY ENABLED)

Symbol

Description

Min

Typ

Max

Units

ttxc

TXC period

Note 7-20

Note 7-21

Note 7-22

tclkh

TXC high time

Note 7-23

Note 7-24

tclkl

TXC low time

Note 7-23

Note 7-24

tsetup

TXD[3:0], TX_CTL setup time to edge of TXC

(at transmitter output)

1.5

thold

TXD[3:0], TX_CTL hold time after edge of TXC

(at transmitter output)

1.5

TXC

TXD[3:0]

TX_CTL

tclkh

tclkl

ttxc

TXD

[3:0]

TXD

[7:4]

TXEN

TXER

thold

tsetup

thold

tsetup

thold

tsetup

thold

tsetup

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