HB28D032MM2 datasheet(72/90 Pages) RENESAS

72 / 90 page

HB28H016/D032/B064/B128MM2

Rev.5.0, Jan. 2003, page 70 of 88

SPI Bus Timing

All timing diagrams use the following schematics and abbreviations:

H: Signal is high (logical ‘1’)

L: Signal is low (logical ‘0’)

X: Don’t care

Z: High impedance state (-> = 1)

*: Repeater

Busy: Busy Token

Command: Command token

Response: Response token

Data block: Data token

All timing values are defined in Table “Timing Values”. The host must keep the clock running for at least

CR clock cycles after receiving the card response.

This restriction applies to both command and data

response tokens.

Command/Response

• Host Command to Card Response - Card is ready

HH L L L

NCS

* * * * * * * * * * * * * * * * * *

L H H H

X X H H H H

6 bytes command

H H

X X X

Datain

H H H H H

* * * * * * *

ZZ Z H H H

H Z Z

Dataout

H H H

1 or 2 bytes response

NEC

NCR

* * * * * * *

• Host Command to Card Response - Card is busy

HL L L

NCS

* * * * * * * * * * * * * * * * * *

L L

LH H

X H H H H

6 bytes command

H H

X X

Datain

HHH HH

HHH H

ZZ HH H H

busy

card response

Dataout

busy

HH H

XX X

LZ Z Z

HHH H

NEC

NDS

NEC

NCR

* * * * * * *

HB28D032MM2 Datasheet(PDF) 72 Page - Renesas Technology Corp

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