FTS64K datasheet(20/44 Pages) FREESCALE

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FTS64K Block User Guide — Version V01.00

Figure 3-2 Flash Clock Divider Register (FCLKDIV)

All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.

FDIVLD — Clock Divider Loaded.

1 = Register has been written to since the last reset.

0 = Register has not been written.

PRDIV8 — Enable Prescaler by 8.

1 = Enables a prescaler by 8, to divide the Flash module input oscillator clock before feeding into

the CLKDIV divider.

0 = The input oscillator clock is directly fed into the FCLKDIV divider.

FDIV[5:0] — Clock Divider Bits.

The combination of PRDIV8 and FDIV[5:0] effectively divides the Flash module input oscillator

clock down to a frequency of 150kHz - 200kHz. The maximum divide ratio is 512. Please refer to

section 4.1.1 for more information.

3.3.2 FSEC — Flash Security Register

This FSEC register holds all bits associated with the device security.

Figure 3-3 Flash Security Register (FSEC)

All bits in the FSEC register are readable but not writable.

FDIVLD

PRDIV8

FDIV5

FDIV4

FDIV3

FDIV2

FDIV1

FDIV0

RESET:

= Unimplemented or Reserved

76543210

KEYEN

NV6

NV5

NV4

NV3

NV2

SEC1

SEC0

Reset:

FFFFFFFF

= Unimplemented or Reserved

Freescale Semiconductor, Inc.

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