MCP3462 datasheet(44/108 Pages) MICROCHIP

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MCP3461/2/4

DS20006180D-page 44

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5.7

Power-on Reset

The analog and digital power supplies are monitored

separately by two Power-on-Reset (POR) monitoring

circuits at all times, except during Full Shutdown mode

(see Section 5.9 “Low-Power Shutdown Modes”).

Each POR circuit has two separate thresholds, one for

the rising voltage supply and one for the falling voltage

supply. They both include hysteresis (the rising

threshold is superior to the falling threshold), so that the

device is tolerant to a certain degree of transient noise

on each power supply.

If any of the two power supply voltages is below its

respective threshold, the POR state is forced internally.

In this state, the SPI interface is disabled and no com-

mand can be executed by the chip. All registers are

cleared and set to their default values.

At power-up, when both power supply voltages are

above the rising thresholds, the device powers up and

the SPI interface is enabled and can handle communi-

cations. Since both thresholds need to be crossed for

the power-up, the power-up sequence is not important

and any power supply voltage can ramp up first. The

detection time for the monitoring circuits (tPOR) is about

1 µs for relatively fast power-up ramp rates. The normal

operation is stopped when any of the falling thresholds

of the two POR monitoring circuits are crossed.

Figure 5-9 illustrates the power-up and power-down

sequences.

If the CS pin is kept logic low during a POR state, a

logic high pulse is necessary to start the first

communication sequence. The CS rising edge will

properly reset the SPI interface and the falling edge will

clear the POR interrupt on the IRQ pin (see

Figure 6-16).

During Full Shutdown mode, the power supply voltages

are not monitored to be able to reach ultra-low power

consumption. The device cannot generate a POR

event interrupt in this mode, except in cases of

extremely low-power supply voltages.

The DVDD and AVDD monitoring thresholds are

different since their respective voltage ranges are

different. The AVDD rising threshold is approximately

1.75V, ±10% and the DVDD is 1.2V, ±10%. The

hysteresis is approximately 150 mV (typical). Proper

decoupling ceramic capacitors (0.1 µF and 10 µF

ceramic) should be placed as close as possible to the

power supply pins (AVDD, DVDD), to provide additional

transient immunity.

In order to ensure a proper power-up sequence, the

ramp rate of DVDD should not exceed 3V/µs when

coming out of the POR state.

Additionally, the user needs to lower the DVDD residual

voltage as much as possible, close to 0V, when the

device is kept for a long time in a POR state (below

DVDD POR threshold) in order to ensure a proper

power-up sequence. The user can verify if the

power-up sequence has been correctly performed by

reading the default state of all the registers in the

or more of the registers do not show the proper default

setting, a new power-up cycle should be launched to

recover from this condition.

FIGURE 5-9:

Power-on Reset Timing Diagram.

POR State

POR Threshold Up

POR Threshold Down

tPOR

Voltage

(AVDD, DVDD)

POR State

Time

Normal Operation

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